The present invention relates to a microprocessor and, more particularly, to an improvement in an instruction decoder unit of a pipelined microprocessor.
A pipelined microprocessor is constructed basically of six units: a bus control unit (BCU) for initiating a bus cycle to perform an instruction fetch operation and operand data read/write operation, an instruction prefetch unit (PFU) for requesting an instruction fetch bus cycle from the BCU to prefetch instructions, an instruction decoder unit (IDU) for decoding the instruction from the PFU and generating data processing information necessary for instruction execution and operand access information necessary for an operand data access, an effective address generator unit (EAG) for calculating an effective address in response to the operand access information, a memory management unit (MMU) for translating the effective address into a real address and requesting an operand data access from the BCU, and an instruction execution unit (EXU) for executing an instruction in response to the data processing information from IDU. These units operate in parallel in a predetermined pipeline processing manner.
In recent years, microprocessors have been required to facilitate software programming. For this purpose, an abundance of instruction formats are prepared, and moreover it is supported than an independent addressing mode can be designated to respective operands. Also in the addressing mode, a plurality of addressing modes are prepared, such as direct/indirect modes, displacement modes, indexed modes and so forth.
However, the support of abundant instruction formats and addressing modes causes instruction decoding time to be prolonged. Specifically, the IDU decodes an instruction to be executed and generates the data processing information and the operand access information in accordance with the decoding sequence determined by the format and the operand addressing mode of that instruction. Therefore, the support of many instruction formats and operand addressing modes prolongs the time for decoding and detecting the format and the operand addressing mode of an instruction to be executed to determine the decoding sequence. The generation of the data processing information and the operand access information is thereby delayed to disturb the pipeline processing operation. The execution efficiency of the microprocessor is thus lowered.